1. Field of the Invention
This invention relates to an improved structure for a transistor and methods for providing such a transistor.
2. Discussion of Prior Art
Over the last two decades there has been much interest in semiconductor devices which operate by restricting the motion of current carriers in one or more directions. In such devices the carriers can only occupy a discrete set of energy levels or sub-bands in one or more dimensions. The motion of the carriers is said to be quantised in the direction of confinement.
In heterojunctions, formed by the joining together of two semiconductor compounds of different band gaps, the carriers are confined to a potential or quantum well. A two dimensional electron gas is formed if the carriers are electrons (or a two dimensional hole gas is formed if the majority carriers are holes).
One particular type of semiconductor device which has been fabricated, typically from GaAs, is the single electron transistor (SET) which was invented in 1987. In this device the two dimensional electron gas is further confined by external gates to form a so called quantum dot which is of such a size that it can hold only a few electrons (typically between 0 and 20). Furthermore, once this number is fixed (by an external contact potential) it does not fluctuate in time by more than one electron.
Such devices are traditionally confined to operate at low temperatures (typically less than liquid nitrogen temperatures) due to the physics which allows them to function. The devices rely on the fact that the quantum dot has a small capacitance, and the energy required to add or remove electrons is quite large. If the device is cooled to low temperatures the electron thermal energy becomes less than the charging energy. Without a significant source-drain voltage bias the electrons cannot travel through the quantum dot. That is, the capacitance of the dot is so small that the addition of a single electron to the potential well significantly increases the electrostatic energy. This is known as Coulomb blockade which suppresses current flow for all gate voltages except to certain values at which the energy of N and N+1 electrons in the quantum dot is approximately the same.
It is an ongoing aim to increase the operating temperature of quantum devices. One method of achieving this is to attempt precise patterning and etching of structures to provide further confinement of the two dimensional electron gas. However, this requires much smaller dimensions and also greater dimensional uniformity than can be realised by traditional lithography and etching. The skilled person will appreciate that using standard optical lithography feature sites of substantially 0.1 xcexcm and registration of substantially xc2x10.3 xcexcm are achievable. Moving to e-beam lithography the feature sizes decrease to 30 nm with a registration of 100 nm.
According to a first aspect of the invention there is provided a transistor having at least one, substantially one-dimensional, elongate conducting means provided by at least a first semiconductor substantially surrounded by a second semiconductor and extending between source and drain electrodes, and in which there is provided at least one further gate electrode in a region of the elongate conducting means.
Such a transistor has the advantage that it is possible to provide confinement for the electrons on a much smaller scale than was previously obtainable. The transistor may be a single electron transistor (SET). The skilled person will appreciate that this is of fundamental importance for producing SETs which operate at higher temperatures; it is possible to reduce the capacitance of the dot by reducing the dimensions of the dot. An electron gas is xe2x80x9chardxe2x80x9d confined in two dimensions by the conducting means.
The conducting means may be provided in a bottom region of a groove. This technique allows the conducting means to be fabricated with smaller dimensions than is possible with lithography techniques.
The first semiconductor may be gallium arsenide (GaAs). The second semiconductor may be aluminium gallium arsenide (AlGaAs). As the skilled person will appreciate these materials are particularly suitable since they are relatively well lattice matched and have a suitably large band gap difference. However, other material systems may equally be possible. For instance indium antimonide (InSb) may be suitable, possibly with gallium nitride (GaN), or possibly with aluminium nitride (AlN).
In one embodiment a groove is formed into a substrate, which may be the same material as the first semiconductor and has a region of the second semiconductor, provided at the base of the groove, and on the sides of the grooves lining the groove. The conducting means may comprise an elongate region of the first semiconductor in a bottom region of the second semiconductor, that is in a bottom region of the lined groove. A layer of a third semiconductor may be provided on top of the first semiconductor. This provides a convenient structure for providing the two dimensional hard confinement. The skilled person will appreciate that this structure could be used with the material systems discussed above. The second and third semi conductors may be substantially the same materials, providing a convenient way of surrounding the first semiconductor with the second.
An anti-oxidation layer may be provided associated with (e.g. on top of) the third semi-conductor layer to prevent oxidation of the third semi-conductor layer. The anti-oxidation layer may be the same material as the first semiconductor. That is the anti-oxidation layer may be GaAs.
The region of the first semiconductor (possibly GaAs) in the bottom of the second semiconductor lined groove may be thought of as a quantum wire. If the wire is sufficiently short, and free from impurities, quantised conduction steps may be seen, which would be indicative of one dimensional conduction. However, fluctuations in the thickness of the wire may be provided and give rise to Coulomb blockade. This Coulomb blockade would give single electron transistor action. In the embodiment where quantised conduction occurs transistor action may also be achievable by the provision of gate structures to provided segregation of the wire into one or more quantum dots. Indeed, multiple gates may be provided to achieve multiple quantum dots. The skilled person will appreciate that prior art transistors generally have 2-dimensional or 3-dimensional conducting means. In the context of this description a 1-dimensional conducting means may be thought of as a wire rather than as a plane, or box.
Preferably the groove is provided within a top region of a mesa structure projecting from a substrate, providing a convenient way of isolating the v-groove from the substrate.
There may be provided more than one conducting means. These may be provided substantially horizontally next to one another and possibly substantially parallel to each other. Alternatively, or additionally, these may be provided substantially vertically above one another. Indeed, a two dimensional grid of conducting means may be provided. Providing more than a single conducting means can have a number of advantages including: it can increase the maximum current handling capability of the device; it can increase the tolerance of the device to defects within the manufacturing process/materials used (The skilled person will appreciate that during crystal growth and device processing defects occur. Having more that a single conducting member can increase the tolerance to these defects); the tolerance of random events, such as photon interactions, can also be increased.
The skilled person will appreciate that the gate electrodes provide soft confinement within the conducting means and effectively provide a quantum dot. There may be provided a plurality of quantum dots along the conducting means. A plurality of dots can be advantageous for a number of reasons. For instance, it has been found that when providing a transistor from a series of dots the performance of the transistor is governed by the dot having the smallest dimensions. The skilled person will realise that the dimensions of a number of quantum dots fabricated in series will be slightly different due to the registration tolerances and that therefore the overall performance of the transistor may be increased (one of the devices may be smaller than expected). Further, it may be possible to form a device which functions similarly to a shift register, with an electron being clocked through each of the quantum dots.
The series of dots may be provided by a plurality of gate electrodes.
A pair of electrodes may be required to provide a single quantum dot. This pair of electrodes may be arranged to provided confinement in a third dimension for charge carriers within the conducting means. That is, the electrodes may be substantially transverse to the conducting means. Each electrode may be capable of causing a peak within the energy bands of the semiconductor of the conducting means such that charge carriers cannot cross the peak without the application of an external bias.
A back gate may be provided in addition to the electrodes so providing a source of charge carriers for the transistor. The back gate may be provided by doping a region of the substrate from which the transistor is fabricated.
Alternatively, or in addition to the provision of a back gate a region of modulation doping may be provided in order to provide charge carriers for the transistor.
A portion of the conducting means may have a crescent shaped cross section, which may be the third semiconductor. The third semiconductor may have a width substantially in the range 10 nm to 60 nm, possibly substantially in the range 20 nm to 50 nm, or possibly in the range 30 nm to 40 nm. The third semiconductor may have a maximum thickness of substantially 1 to 10 nm, possibly substantially 3 to 7 nm.
The materials used to provide the conducting means may have a band gap difference of substantially at least 0.3 eV, possibly at least 0.5 eV or possibly at least 1 eV.
According to a second aspect of the invention there is provided a method of providing a transistor comprising providing a substantially one-dimensional elongate conducting means by providing an elongate region of first semiconductor substantially surrounded by a second semiconductor providing a source electrode at a first end region of the conducting means and a drain electrode at a second end region of the conducting means, and providing at least one further gate electrode in a region of the conducting means.
Such a method is advantageous because it may provide a transistor with better operating characteristics than has previously been achievable (e.g. operating temperature may be higher, etc.). The transistor may be a single electron transistor (SET).
The method may comprise fabricating a groove in a substrate. The groove may be formed by an anisotropic etch, may be using a sulphuric/peroxide etch.
Prior to the etching of the groove in the first semiconductor an n+ epilayer may be grown onto the substrate. The groove may be formed in this epilayer. The epilayer may have a thickness of substantially 5 xcexcm. The epilayer is advantageous because it provides a back gate which supplies charge carriers to the transistor.
In an alternative and perhaps preferred embodiment a pxe2x88x92 doped region is grown in a top region of the n+ epilayer and the groove formed in the pxe2x88x92 doped region. This is perhaps preferred because it may allow a wire formed in the groove to be more readily insulated from the n+ epilayer and thus help to prevent shorting between the n+ epilayer and the wire.
The groove may be lined with a second semiconductor. The first semiconductor may be provided in a bottom region of the lined groove. A third semi-conductor may be provided, covering the first semi-conductor. These steps may provide the elongate conducting means (or wire) from the first semi-conductor surrounded by second and third semiconductor. An advantage of using these steps is that the dimensions of the conducting means can be made smaller than by using prior art methods. The substrate and first semiconductors may be substantially the same material. The second and third semi-conductors may be substantially the same material. This structure is advantageous since it provides two neighbouring heterojunctions surrounding the conducting means and provides hard confinement for carriers within the conducting means, i.e. hard confinement in two dimensions.
The skilled person will appreciate that the if the GaAs/AlGaAs material system is used that when depositing GaAs onto AlGaAs the GaAs is preferentially deposited onto (001) planes due to diffusion of the GaAs to the (001) planes. The method may comprise arranging the groove in the substrate such that the second semiconductor is grown substantially only in a bottom region of the groove. This may comprise arranging for the base of the groove to extend substantially in a (001) plane. The skilled person will appreciate that this is possible with any material system that shows preferential deposition of one material on certain planes of the other material. However, the first material may be GaAs and the second material may be AlGaAs. The substrate may be GaAs. The groove may be arranged such that the walls of the groove lies substantially along the (111) planes of the semiconductor.
It is an advantage of this method that the first semiconductor can be provided with dimensions which are smaller than is possible using standard patterning and etching techniques. Therefore, it is possible using this method to provide hard confinement in two dimensions. This has previously not been possible without the use of gate electrodes to provide (or increase) the confinement in the second dimension.
A further layer, an anti-oxidation layer, may be provided over the third semi-conductor layer and prevents oxidation of the third semi-conductor layer. The anti-oxidation layer may be the same material as first semiconductor.
The method may rely on process variations within the fabrication steps of the conducting means to provide quantum dots. As the skilled person will appreciate there are process variations within any device fabrication process. These variations may cause slight variations in the thickness of the conducting means, leading to the formation of quantum dots.
In one embodiment the groove in the substrate is formed slightly off axis from the desired plane. This causes sawxe2x80x94tooth like variation in the thickness of the conducting means, which may provide quantum dots along the length of the conducting means. The skilled person will appreciate that the degree that the groove is formed off axis will determine the period of the saw tooth.
We may choose to incline the base of the groove to the (001) Plane by a few degrees, for example substantially in the range 0-10xc2x0, or 0-6xc2x0, or 0-3xc2x0, or 0 to 1xc2x0 or 2xc2x0.
According to a third aspect of the invention there is provided a groove within a substrate having a first semiconductor provided in a bottom region of the groove and at least one electrode being provided in association with the groove.
This structure may provide useful in a number of electronic devices.
According to a fourth aspect of the invention there may be provided a method of fabricating an elongate conducting means comprising a first semiconductor substantially surrounded by a second semiconductor the method comprising fabricating a groove in a substrate and depositing a first semiconductor into a bottom region of the groove, the method further comprising providing electrodes in association with the conducting means adapted to control the flow of charge carriers through the conducting means.